2024-03-29T12:37:09Zhttps://eprints.lib.hokudai.ac.jp/dspace-oai/requestoai:eprints.lib.hokudai.ac.jp:2115/474902022-11-17T02:08:08Zhdl_2115_20053hdl_2115_145Minimum-Width Method of Variable Ordering for Binary Decision Diagrams1000010374612Minato, Shin-ichiopen accesscopyright©1992 IEICEbinary decision diagramsboolean functionlogic synthesisvariable ordering007PAPER: Special Section on the 4th Karuizawa Workshop on Circuits and SystemsBinary Decision Diagrams (BDDs) and Shared Binary Decision Diagrams (SBDDs), which are improved BDDs, are useful for implementing VLSI logic design systems. Recently, these representations, which are graph representations of Boolean functions, have become popular because of their efficiency in terms of time and space. The forms of the BDD vary with the order of the input variables though they represent the same function. The size of the graphs greatly depends on the order. The variable ordering algorithm is one of the most important issues in the application of BDDs. In this paper, we consider methods which reduce the graph size by reordering input variables on a given BDD with a certain variable order. We propose the Minimum-Width Method which gives a considerably good order in a practicable time and space. In the method, the order is determined by width of BDDs as a cost function. In addition, we show the effect of combining our method with the local search method, and also describe the improvement using the threshold. Experimental results show that our method can reduce the size of BDDs remarkably for most examples. The method needs no additional information, such as the topological information of the circuit. The results can be a measure for evaluation of other ordering methods.電子情報通信学会1992-03-20engjournal articleVoRhttp://hdl.handle.net/2115/474900916-8508IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer SciencesE75A3392399https://eprints.lib.hokudai.ac.jp/dspace/bitstream/2115/47490/3/62_IEICE75_392.pdfapplication/pdf1.82 MB1992-03-20