2024-03-29T05:02:06Zhttps://eprints.lib.hokudai.ac.jp/dspace-oai/requestoai:eprints.lib.hokudai.ac.jp:2115/574482022-11-17T02:08:08Zhdl_2115_20053hdl_2115_145Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growthTomioka, KatsuhiroFukui, TakashiIII-V nanowiresepitaxyFETtunnel FET548We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.IOP PublishingJournal Articleapplication/pdfhttp://hdl.handle.net/2115/57448https://eprints.lib.hokudai.ac.jp/dspace/bitstream/2115/57448/1/0022-3727_47_39_394001.pdf0022-3727Journal of Physics D: Applied Physics47393940012014-10-01enginfo:doi/10.1088/0022-3727/47/39/394001http://creativecommons.org/licenses/by/3.0publisher