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VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver

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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/47066

Title: VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver
Authors: Yoshizawa, Shingo Browse this author →KAKEN DB
Ikeuchi, Hirokazu Browse this author
Miyanaga, Yoshikazu Browse this author →KAKEN DB
Keywords: wireless communications
MIMO-OFDM
MIMO detection
MMSE
Issue Date: 1-Jan-2011
Publisher: Institute of Electronics, Information and Communication Engineers
Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E94-A
Issue: 1
Start Page: 324
End Page: 331
Publisher DOI: 10.1587/transfun.E94.A.324
Abstract: MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.
Rights: copyright © 2011 IEICE
Relation: http://search.ieice.org/
Type: article
URI: http://hdl.handle.net/2115/47066
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 吉澤 真吾

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