open access

https://hdl.handle.net/2115/39736

An Algorithm for Bit-Serial Addition of SPT Numbers for Multiplierless Realization of Adaptive Equalizers

英語

2009-10-04

Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference, International Organizing Committee

Proceedings : APSIPA ASC 2009 : Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference

438-440

APSIPA ASC 2009: Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference. 4-7 October 2009. Sapporo, Japan. Poster session: Signal Processing Theory and Methods I (6 October 2009).

The "sum of power of two (SPT)" is an effective format to represent multipliers in a digital filter which reduces the complexity of multiplication to a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees occurrence of at least one zero between every two nonzero SPT bits. This paper presents a novel algorithm for bit serial addition of two numbers, each given in canonic SPT form, to produce a result also in canonic SPT. The proposed algorithm uses the properties of canonic SPT numbers effectively, resulting in considerable reduction of the hardware complexity of the bit serial adder. The algorithm is particularly useful for multiplier free realization of adaptive filters and equalizers, where the current weight vector and the update term, both presumed to be given in canonic SPT, are required to be added in a way that retains the canonic SPT format for the updated weight vector.

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