A 300 nW, 15 ppm/℃, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Ueno, Ken; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

A 300 nW, 15 ppm/℃, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Ueno, Ken; Hirose, Tetsuya; Asai, Tetsuya et al.

IEEE Journal of Solid-State Circuits, 2009, 44(7), 2047-2054

Permalink : https://hdl.handle.net/2115/39949

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論文情報

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アクセス権	open access
URI	https://hdl.handle.net/2115/39949
タイトル	A 300 nW, 15 ppm/℃, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
その他のタイトル	A 300 nW, 15 ppm/degC, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
著者	Ueno, Ken ; Hirose, Tetsuya ; Asai, Tetsuya ; Amemiya, Yoshihito
著者名 Ueno, Ken 著者別名 Ueno, K.
著者名 Hirose, Tetsuya 著者別名 Hirose, T.
著者名 Asai, Tetsuya 著者別名 Asai, T.
e-Rad_Researcher 80250489 著者名 Amemiya, Yoshihito 著者別名 Amemiya, Y.
言語	英語
キーワード	CMOS
	voltage reference
	ultra-low power
	subthreshold
	weak inversion
	process variation
	die-to-die variation
	power-aware LSIs
発行日	2009-07
出版者	IEEE
収録物名	IEEE Journal of Solid-State Circuits
巻(号)	44(7)
ページ	2047-2054
抄録	A low-power CMOS voltage reference was developed using a 0.35 μm standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/℃ at best and 15 ppm/℃ on average, in a range from -20 to 80 ℃. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 μW at 80 ℃. The chip area was 0.05 mm2. Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
資源タイプ	学術雑誌論文
出版タイプ	Version of Record
権利情報	© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
PISSN	0018-9200
NCID	AA00667434
関連情報 (isIdenticalTo)	出版社版DOI https://doi.org/10.1109/JSSC.2009.2021922