An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tsugita, Yusuke; Ueno, Ken; Hirose, Tetsuya et al.

IEICE Transactions on Electronics, 2010, E93C(6), 835-841

Permalink : https://hdl.handle.net/2115/44313

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アクセス権
open access
URI
https://hdl.handle.net/2115/44313
タイトル
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs
著者
Tsugita, Yusuke ; Ueno, Ken ; Hirose, Tetsuya ; Asai, Tetsuya ; Amemiya, Yoshihito
著者名
Tsugita, Yusuke
著者名
Ueno, Ken
著者名
Hirose, Tetsuya
著者名
Asai, Tetsuya
著者名
Amemiya, Yoshihito
言語
英語
キーワード
digital circuits
threshold voltage variation
compensation circuit
PVT variation
発行日
2010-06-01
出版者
IEICE: Institute of Electronics, Information and Communication Engineers
収録物名
IEICE Transactions on Electronics
巻(号)
E93C(6)
ページ
835-841
抄録
An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-μm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
資源タイプ
学術雑誌論文
出版タイプ
Version of Record
権利情報
copyright©2010 IEICE
PISSN
0916-8524
関連情報
URI
http://search.ieice.org/
関連情報 (isIdenticalTo)
出版社版DOI
https://doi.org/10.1587/transele.E93.C.835