open access

https://hdl.handle.net/2115/47066

VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver

英語

MMSE

2011-01-01

Institute of Electronics, Information and Communication Engineers

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

E94-A(1)

324-331

MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.

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