DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction

YAMASHITA, Shigeru; MINATO, Shin-ichi; MILLER, D. Michael

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2008, E91-A(12), 3793-3802

Permalink : https://hdl.handle.net/2115/47392

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論文情報

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アクセス権
open access
URI
https://hdl.handle.net/2115/47392
タイトル
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
著者
YAMASHITA, Shigeru ; MINATO, Shin-ichi ; MILLER, D. Michael
著者名
YAMASHITA, Shigeru
e-Rad_Researcher
10374612
著者名
MINATO, Shin-ichi
著者名
MILLER, D. Michael
言語
英語
キーワード
quantum circuit
verification
decision diagram
発行日
2008-12
出版者
電子情報通信学会
収録物名
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻(号)
E91-A(12)
ページ
3793-3802
抄録
Recently much attention has been paid to quantum circuit design to prepare for the future “quantum computation era.” Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.
資源タイプ
学術雑誌論文
出版タイプ
Version of Record
権利情報
copyright©2008 IEICE
PISSN
0916-8508
EISSN
1745-1337
関連情報 (isIdenticalTo)
出版社版DOI
https://doi.org/10.1093/ietfec/e91-a.12.3793