open access

https://hdl.handle.net/2115/47468

Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams

英語

logic synthesis

1993-06-25

電子情報通信学会

IEICE transactions on fundamentals of electronics, communications and computer sciences

E76(A6)

967-973

Manipulation of Boolean functions is one of the most important techniques for implementing of VLSI logic design systems. This paper presents a fast method for generating prime-irredundant covers from Binary Decision Diagrams (BDDs), which are efficient representation of Boolean functions. Prime-irredundant covers are forms in which each cube is a prime implicant and no cube can be eliminated. This new method generates compact cube sets from BDDs directly, in contrast to the conventional cube set reduction algorithms, which commonly manipulate redundant cube sets or truth tables. Our method is based on the idea of a recursive operator, proposed by Morreale. Morreale's algorithm is also based on cube set manipulation. We found that the algorithm can be improved and rearranged to fit BDD operations efficiently. The experimental results demonstrate that our method is efficient in terms of time and space. In practical time, we can generate cube sets consisting of more than 1,000,000 literals from multi-level logic circuits which have never previously been flattened into two-level logics. Our method is more than 10 times faster than ESPRESSO in largescale examples. It gives quasi-minimum numbers of cubes and literals. This method should find many useful applications in logic design systems.

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