Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

Matsumoto, Chizu; Hamamura, Yuichi; Nakao, Michinobu et al.

IEICE Transactions on Electronics, 2013, E96.C(1), 108-114

Permalink : https://hdl.handle.net/2115/52057

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アクセス権
open access
URI
https://hdl.handle.net/2115/52057
タイトル
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
著者
Matsumoto, Chizu ; Hamamura, Yuichi ; Nakao, Michinobu ; Yamasaki, Kaname ; Saito, Yoshikazu ; Kaneko, Shun'ichi
著者名
Matsumoto, Chizu
著者名
Hamamura, Yuichi
著者名
Nakao, Michinobu
著者名
Yamasaki, Kaname
著者名
Saito, Yoshikazu
e-Rad_Researcher
50134789
著者名
Kaneko, Shun'ichi
言語
英語
キーワード
random access memory
system-on-chip
redundancy
fuse
発行日
2013-01-01
出版者
Institute of Electronics, Information and Communication Engineers
収録物名
IEICE Transactions on Electronics
巻(号)
E96.C(1)
ページ
108-114
抄録
Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.
資源タイプ
学術雑誌論文
出版タイプ
Version of Record
権利情報
Copyright © 2013 The Institute of Electronics, Information and Communication Engineers
PISSN
0916-8524
関連情報
URI
http://search.ieice.org/
関連情報 (isIdenticalTo)
出版社版DOI
https://doi.org/10.1587/transele.E96.C.108