A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

Miyoshi, Yoshihito; Nakajima, Fumito; Motohisa, Junichi; Fukuia, Takashi

A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

Miyoshi, Yoshihito; Nakajima, Fumito; Motohisa, Junichi et al.

Applied Physics Letters, 2005, 87(3), 033501

Permalink : https://hdl.handle.net/2115/5505

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アクセス権	open access
URI	https://hdl.handle.net/2115/5505
タイトル	A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy
著者	Miyoshi, Yoshihito ; Nakajima, Fumito ; Motohisa, Junichi ; Fukuia, Takashi
著者名 Miyoshi, Yoshihito
著者名 Nakajima, Fumito
e-Rad_Researcher 60212263 著者名 Motohisa, Junichi 本久, 順一
著者名 Fukuia, Takashi
言語	英語
発行日	2005-07-18
出版者	American Institute of Physics
収録物名	Applied Physics Letters
巻(号)	87(3)
ページ	033501
抄録	We demonstrate single-electron operation of a 1 bit adder circuit using GaAs single-electron tunneling transistors (SETs). GaAs dot and wire coupled structures for the fabrication of SETs were grown by a selective-area metalorganic vapor-phase epitaxy technique. The logic circuit was realized based on a binary decision diagram architecture using Coulomb blockade (CB) in GaAs dots and switching operations were achieved in a single-electron mode because of the CB effects. Through this architecture, a 1 bit adder circuit was realized with three SETs, two of which were for AND logic and one with two input gates for exclusive OR (XOR). Both AND and XOR operations were demonstrated at 1.9 K, which indicated successful fabrication of the 1 bit adder.
資源タイプ	学術雑誌論文
出版タイプ	Version of Record
権利情報	Copyright © 2005 American Institute of Physics
PISSN	0003-6951
関連情報 (isIdenticalTo)	出版社版DOI https://doi.org/10.1063/1.1992665