Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

Takahagi, Kazuhiro; Matsushita, Hiromichi; Iida, Tomoki; Ikebe, Masayuki; Amemiya, Yoshihito; Sano, Eiichi

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

Takahagi, Kazuhiro; Matsushita, Hiromichi; Iida, Tomoki et al.

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 75(2), 199-205

Permalink : https://hdl.handle.net/2115/55277

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論文情報

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アクセス権	open access
URI	https://hdl.handle.net/2115/55277
タイトル	Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks
著者	Takahagi, Kazuhiro ; Matsushita, Hiromichi ; Iida, Tomoki ; Ikebe, Masayuki ; Amemiya, Yoshihito ; Sano, Eiichi
著者名 Takahagi, Kazuhiro
著者名 Matsushita, Hiromichi
著者名 Iida, Tomoki
e-Rad_Researcher 20374613 著者名 Ikebe, Masayuki
e-Rad_Researcher 80250489 著者名 Amemiya, Yoshihito
e-Rad_Researcher 10333650 著者名 Sano, Eiichi
言語	英語
キーワード	Wake-up receiver
	Envelope detector
	High-gain amplifier
	Clock and data recovery
	Subthreshold operation
発行日	2013-05
出版者	SPRINGER
収録物名	ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
巻(号)	75(2)
ページ	199-205
抄録	We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-mu m CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of -47.2 dBm while consuming only 6.8 mu W from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.
資源タイプ	学術雑誌論文
出版タイプ	Accepted Manuscript
権利情報	The final publication is available at link.springer.com
PISSN	0925-1030
関連情報 (isVersionOf)	出版社版DOI https://doi.org/10.1007/s10470-012-9929-1