open access

https://hdl.handle.net/2115/70061

Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network

英語

noise

2017-05

Taylor & Francis

International journal of parallel, emergent and distributed systems

32(3)

287-294

Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger.

学術雑誌論文

Accepted Manuscript

This is an Accepted Manuscript of an article published by Taylor & Francis in International journal of parallel, emergent and distributed systems on May 2017, available online: http://www.tandfonline.com/10.1080/17445760.2016.1201673.

1744-5760