open access

https://hdl.handle.net/2115/39752

Hardware Implementation of Adaboost-based Sign Recognition for Miniature Robot

英語

2009-10-04

Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference, International Organizing Committee

Proceedings : APSIPA ASC 2009 : Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference

490-493

APSIPA ASC 2009: Asia-Pacific Signal and Information Processing Association, 2009 Annual Summit and Conference. 4-7 October 2009. Sapporo, Japan. Oral session: Intelligent Systems for Multimedia Signal Processing (6 October 2009).

In this paper, we propose a hardware implementation of a sign recognition system for miniature robot based on Adaboost algorithm. We describe the hardware design techniques including preprocessing, pipelined feature generator and classifier processing. The proposed pipelined architecture reduces working memory significantly compared to straightforward implementation that requires large frame memory. The architecture has been designed by using System Verilog and Verilog-HDL. Implementation result shows that FPGA lcell usage of Altera Cyclone-III(EP3C55F) is 44%. Evaluation result shows that the error rate is 6% or less, and processing time is within video frame rate.

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