open access

https://hdl.handle.net/2115/48438

Formal Verification of UML-based Specifications

英語

2011-06

ERATO湊離散構造処理系プロジェクト

ERATOセミナ2010 : No.34. 2011年1月31日

In the recent years, researchers started to enrich the classical textbook specification of embedded systems by more formal descriptions such as the Unified Modeling Language (UML). This enables to lift the starting point for verifcation techniques to the specification level and leads to an improved design flow, where crucial flaws can be detected, even if no executable implementation is available. However, research on e cient solving techniques for the respective verification tasks is just at the beginning. In the talk, the improved design flow based on specifications enriched with formal descriptions is introduced. We illustrate how early design flaws become evident within this flow and briefly review algorithms aimed at detecting them. Furthermore, first experimental results are presented. Overall, the aim of the talk is to provide an introduction into this emerging area and to present first results.

会議発表資料

Not Applicable (or Unknown)

2186-1846