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Efficiency-Centric Hardware Accelerator for Deep Neural Network Inference [an abstract of dissertation and a summary of dissertation review]

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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/78434

Title: Efficiency-Centric Hardware Accelerator for Deep Neural Network Inference [an abstract of dissertation and a summary of dissertation review]
Other Titles: 深層ニューラルネットワーク向け高効率HWアクセラレータに関する研究 [論文内容及び審査の要旨]
Authors: 植吉, 晃大 Browse this author
Issue Date: 25-Mar-2020
Conffering University: 北海道大学
Degree Report Number: 甲第14129号
Degree Level: 博士
Degree Discipline: 工学
Examination Committee Members: (主査) 教授 浅井 哲也, 教授 富田 章久, 教授 葛西 誠也(量子集積エレクトロニクス研究センター), 教授 池辺 将之(量子集積エレクトロニクス研究センター)
Degree Affiliation: 情報科学研究科(情報エレクトロニクス専攻)
Rights: https://creativecommons.org/licenses/by/4.0/
Type: theses (doctoral - abstract and summary of review)
URI: http://hdl.handle.net/2115/78434
Appears in Collections:課程博士 (Doctorate by way of Advanced Course) > 情報科学院(Graduate School of Information Science and Technology)
学位論文 (Theses) > 博士 (工学)

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