Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HENTs Having a Silicon Interface Control Layer

XIE, Yong-Gui; KASAI, Seiya; TAKAHASHI, Hiroshi; JIANG, Chao; HASEGAWA, Hideki


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Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HENTs Having a Silicon Interface Control Layer

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Title:	Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HENTs Having a Silicon Interface Control Layer
Authors:	XIE, Yong-Gui Browse this author
	KASAI, Seiya Browse this author →KAKEN DB
	TAKAHASHI, Hiroshi Browse this author
	JIANG, Chao Browse this author
	HASEGAWA, Hideki Browse this author
Keywords:	insulated gate
	PHEMT
	InGaAs
	interface control
	Fermi level pinning
Issue Date:	Oct-2001
Publisher:	IEICE
Journal Title:	IEICE Transactions on Electronics
Volume:	E84-C
Issue:	10
Start Page:	1335
End Page:	1343
Abstract:	A novel InGaAs/InAlAs insulated gate (IG) pseudomorphic high electron mobility transistor (PHEMT) having a silicon interface control layer (Si ICL) is successfully fabricated and characterized. Systematic efforts to characterize and optimize the insulated gate structure and the PHEMT fabrication process were made by using in-situ X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques. This led to successful fabrication of a novel IG-PHEMT showing excellent stable DC characteristics with a good pinch off and a high transconductance (177 mS/mm), very small gate leakage currents, very high gate breakdown voltages (about 40 V) and respectable RF characteristics fT = 9 GHz and fmax=38 GHz.
Rights:	Copyright (c) 2001 IEICE (許諾番号 : 06RB0100)
Relation:	http://search.ieice.org/
Type:	article
URI:	http://hdl.handle.net/2115/14551
Appears in Collections:	情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 葛西誠也

OAI-PMH ( junii2 , jpcoar_1.0 )

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