トランジスタ論理回路の遅延時間について


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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/40995

Title:	トランジスタ論理回路の遅延時間について
Other Titles:	Delay Time of Transistor Logic Circuits
Authors:	安住, 和彦¹ Browse this author
Authors:	黒部, 貞一² Browse this author
Authors(alt):	Azumi, Kazuhiko¹
Authors(alt):	Kurobe, Teiichi²
Issue Date:	31-Oct-1970
Publisher:	北海道大学
Journal Title:	北海道大學工學部研究報告
Journal Title(alt):	Bulletin of the Faculty of Engineering, Hokkaido University
Volume:	57
Start Page:	141
End Page:	152
Type:	bulletin (article)
URI:	http://hdl.handle.net/2115/40995
Appears in Collections:	北海道大学工学部研究報告 = Bulletin of the Faculty of Engineering, Hokkaido University > No.57

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