トランジスタ多段回路の遅延時間および立上り時間の相加性について


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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/41024

Title:	トランジスタ多段回路の遅延時間および立上り時間の相加性について
Other Titles:	Additivity of Delay Time and Rise Time in Multistage Transistor Circuits
Authors:	黒部, 貞一¹ Browse this author
Authors:	安住, 和彦² Browse this author
Authors(alt):	Kurobe, Teiichi¹
Authors(alt):	Azumi, Kazuhiko²
Issue Date:	10-Mar-1971
Publisher:	北海道大学
Journal Title:	北海道大學工學部研究報告
Journal Title(alt):	Bulletin of the Faculty of Engineering, Hokkaido University
Volume:	59
Start Page:	39
End Page:	43
Type:	bulletin (article)
URI:	http://hdl.handle.net/2115/41024
Appears in Collections:	北海道大学工学部研究報告 = Bulletin of the Faculty of Engineering, Hokkaido University > No.59

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