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北海道大学工学部研究報告 = Bulletin of the Faculty of Engineering, Hokkaido University >
No.77 >

集積回路の最適設計法について : MOS4素子メモリの最適設計

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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/41309

Title: 集積回路の最適設計法について : MOS4素子メモリの最適設計
Other Titles: Optimization of IC : Optimization of MOS 4-Transistor Memory
Authors: 阿久津, 孝雄1 Browse this author
下野, 哲雄2 Browse this author
小川, 吉彦3 Browse this author
黒部, 貞一4 Browse this author
Authors(alt): Akutsu, Takao1
Simono, Tetsuo2
Ogawa, Yoshihiko3
Kurobe, Teiichi4
Issue Date: 4-Oct-1975
Publisher: 北海道大学
Journal Title: 北海道大學工學部研究報告
Journal Title(alt): Bulletin of the Faculty of Engineering, Hokkaido University
Volume: 77
Start Page: 79
End Page: 89
Type: bulletin (article)
URI: http://hdl.handle.net/2115/41309
Appears in Collections:北海道大学工学部研究報告 = Bulletin of the Faculty of Engineering, Hokkaido University > No.77

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