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An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

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Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/44313

Title: An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs
Authors: Tsugita, Yusuke Browse this author
Ueno, Ken Browse this author
Hirose, Tetsuya Browse this author
Asai, Tetsuya Browse this author
Amemiya, Yoshihito Browse this author
Keywords: digital circuits
threshold voltage variation
compensation circuit
PVT variation
Issue Date: 1-Jun-2010
Publisher: IEICE: Institute of Electronics, Information and Communication Engineers
Journal Title: IEICE Transactions on Electronics
Volume: E93C
Issue: 6
Start Page: 835
End Page: 841
Publisher DOI: 10.1587/transele.E93.C.835
Abstract: An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-μm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
Rights: copyright©2010 IEICE
Relation: http://search.ieice.org/
Type: article
URI: http://hdl.handle.net/2115/44313
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 雨宮 好仁

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