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Hokkaido University Collection of Scholarly and Academic Papers >
Graduate School of Information Science and Technology / Faculty of Information Science and Technology >
Peer-reviewed Journal Articles, etc >
A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions
| Title: | A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions |
| Authors: | Kaneta, Yusaku Browse this author | | Yoshizawa, Shingo Browse this author | | Minato, Shin-ichi Browse this author →KAKEN DB | | Arimura, Hiroki Browse this author →KAKEN DB | | Miyanaga, Yoshikazu Browse this author →KAKEN DB |
| Keywords: | FPGA | | string matching | | regular expression matching | | bit-parallel algorithm | | event stream processing |
| Issue Date: | 1-Jul-2012 |
| Publisher: | Institute of Electronics, Information and Communication Engineers |
| Journal Title: | IEICE Transactions on Information and Systems |
| Volume: | E95D |
| Issue: | 7 |
| Start Page: | 1847 |
| End Page: | 1857 |
| Publisher DOI: | 10.1587/transinf.E95.D.1847 |
| Abstract: | In this paper, we propose a novel architecture for large-scale regular expression matching, called dynamically reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA), which allows dynamic loading of regular expressions on-the-fly as well as efficient pattern matching for fast data streams. This is the first dynamically reconfigurable hardware with guaranteed performance for the class of extended patterns, which is a subclass of regular expressions consisting of union of characters and its repeat. This class allows operators such as character classes, gaps, optional characters, and bounded and unbounded repeats of character classes. The key to our architecture is the use of bit-parallel pattern matching approach, in which the information of an input non-deterministic finite automaton (NFA) is first compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using bitwise Boolean and arithmetic operations consuming one input character per clock regardless of the actual contents of an input text. Experimental results showed that our hardwares for both string and extended patterns were comparable to previous dynamically reconfigurable hardwares in their performances. |
| Rights: | Copyright © 2012 The Institute of Electronics, Information and Communication Engineers |
| Relation: | http://search.ieice.org/ |
| Type: | article |
| URI: | http://hdl.handle.net/2115/49779 |
| Appears in Collections: | 情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 有村 博紀
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