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Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Title: | Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs |
Authors: | Matsumoto, Chizu Browse this author | Hamamura, Yuichi Browse this author | Nakao, Michinobu Browse this author | Yamasaki, Kaname Browse this author | Saito, Yoshikazu Browse this author | Kaneko, Shun'ichi Browse this author →KAKEN DB |
Keywords: | random access memory | system-on-chip | redundancy | fuse |
Issue Date: | 1-Jan-2013 |
Publisher: | Institute of Electronics, Information and Communication Engineers |
Journal Title: | IEICE Transactions on Electronics |
Volume: | E96.C |
Issue: | 1 |
Start Page: | 108 |
End Page: | 114 |
Publisher DOI: | 10.1587/transele.E96.C.108 |
Abstract: | Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products. |
Rights: | Copyright © 2013 The Institute of Electronics, Information and Communication Engineers |
Relation: | http://search.ieice.org/ |
Type: | article |
URI: | http://hdl.handle.net/2115/52057 |
Appears in Collections: | 情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 金子 俊一
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