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Advances in Steep-Slope Tunnel FETs

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タイトル: Advances in Steep-Slope Tunnel FETs
著者: Tomioka, Katsuhiro 著作を一覧する
Motohisa, Junichi 著作を一覧する
Fukui, Takashi 著作を一覧する
キーワード: Tunneling FET
III-V compound semiconductors
nanowires
heterojunction
発行日: 2016年 9月
出版者: IEEE (Institute of Electrical and Electronics Engineers)
引用: 2016 46th European Solid-State Device Research Conference (ESSDERC),978-1-5090-2969-3
開始ページ: 397
終了ページ: 402
出版社 DOI: 10.1109/ESSDERC.2016.7599670
抄録: Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III-V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III-V nanowires (NWs) on Si, are promising tunnel junction for achieving steep subthreshold slope (SS). The III-V/Si heterojunction inherently forms abrupt junctions regardless of precise doping technique because the band discontinuity is determined by only the offset of III-V and Si, and depletion region can be controlled by the III-V MOS structure. Thus, good gate-electrostatic control with a large internal electrical field for modulation of tunnel transport can be achieved. Here we repot on recent advances in the vertical TFETs using the III-V NW/Si heterojunction with surrounding-gate architecture and demonstrate steep-SS behavior and very low parasitic leakage current.
Rights: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
資料タイプ: proceedings (author version)
URI: http://hdl.handle.net/2115/64541
出現コレクション:雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

提供者: 冨岡 克広

 

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