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Hokkaido University Collection of Scholarly and Academic Papers >
Graduate School of Information Science and Technology / Faculty of Information Science and Technology >
Peer-reviewed Journal Articles, etc >
An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors
| Title: | An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors |
| Authors: | Hida, Itaru Browse this author | | Takamaeda-Yamazaki, Shinya Browse this author | | Ikebe, Masayuki Browse this author →KAKEN DB | | Motomura, Masato Browse this author | | Asai, Tetsuya Browse this author →KAKEN DB |
| Keywords: | dynamic branch prediction | | supervised machine learning | | naive Bayes classifier | | energy-efficient microprocessor | | low-power architecture | | CMOS digital circuit |
| Issue Date: | 2017 |
| Publisher: | 電子情報通信学会 |
| Journal Title: | Nonlinear Theory and Its Applications, IEICE |
| Volume: | 8 |
| Issue: | 3 |
| Start Page: | 235 |
| End Page: | 245 |
| Publisher DOI: | 10.1587/nolta.8.235 |
| Abstract: | In this paper, we propose a Bayesian branch-prediction circuit, consisting of an instruction-feature extractor and a naive Bayes classifier (NBC), as a machine learning approach for branch prediction. A branch predictor predicts the outcome of a branch instruction by analyzing the pattern of the previous branch outcome. In other words, branch prediction can be viewed as a type of pattern recognition problem, and such problems are often solved using neural networks. A perceptron branch predictor has already been proposed as one example of a neural branch prediction architecture, which predicts the next branch outcome by using past branch history to form feature vectors. The proposed circuit is constructed by replacing the arithmetic unit (neurons) in conventional neural branch predictors with an NBC. By introducing an approximate Bayesian computation and its parallel architectures, the NBC circuit completes branch prediction within two clock cycles per instruction. This constitutes a suitable replacement for conventional branch predictors in modern pipelined reduced instruction set computing microprocessors. |
| Rights: | Copyright ©2017 The Institute of Electronics, Information and Communication Engineers |
| Type: | article |
| URI: | http://hdl.handle.net/2115/68659 |
| Appears in Collections: | 情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 肥田 格
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