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Hokkaido University Collection of Scholarly and Academic Papers >
Graduate School of Information Science and Technology / Faculty of Information Science and Technology >
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A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology
| Title: | A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology |
| Other Titles: | BDD-based 2-bit Arithmetic Logic Unit on GaAs-based Regular Nanowire Network with Hexagonal Topology |
| Authors: | Zhao, Hong-Quan Browse this author | | Kasai, Seiya Browse this author →KAKEN DB | | Shiratori, Yuta Browse this author | | Hashizume, Tamotsu Browse this author |
| Keywords: | Arithmetic logic unit (ALU) | | nanowire network | | binary decision diagram (BDD) | | Schottky wrap gate (WPG) | | GaAs |
| Issue Date: | 17-Jun-2009 |
| Journal Title: | Nanotechnology |
| Volume: | 20 |
| Issue: | 24 |
| Start Page: | 245203 |
| Publisher DOI: | 10.1088/0957-4484/20/24/245203 |
| PMID: | 19468164 |
| Abstract: | A 2-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The 4-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate-control of nanowires. The fabricated circuit integrating 32 node devices exhibits correct output waveforms at room temperature allowing for threshold voltage variation. |
| Rights: | This is an author-created, un-copyedited version of an article accepted for publication in Nanotechnology. IOP Publishing Ltd is not responsible for any errors or omissions in this version of the manuscript or any version derived from it. The definitive publisher authenticated version is available online at http://dx.doi.org/10.1088/0957-4484/20/24/245203. |
| Type: | article (author version) |
| URI: | http://hdl.handle.net/2115/38653 |
| Appears in Collections: | 情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 葛西 誠也
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