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Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

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Title: Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
Authors: Ogawa, Taichi Browse this author
Hirose, Tetsuya Browse this author
Asai, Tetsuya Browse this author
Amemiya, Yoshihito Browse this author
Keywords: subthreshold
MOS
circuit
threshold logic
majority logic
gate
current mode
Issue Date: 1-Feb-2009
Publisher: IEICE - The Institute of Electronics, Information and Communication Engineers
Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E92-A
Issue: 2
Start Page: 436
End Page: 442
Publisher DOI: 10.1587/transfun.E92.A.436
Abstract: A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
Rights: Copyright © 2009 The Institute of Electronics, Information and Communication Engineers
Relation: http://search.ieice.or.jp/
Type: article
URI: http://hdl.handle.net/2115/38896
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 雨宮 好仁

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