HUSCAP logo Hokkaido Univ. logo

Hokkaido University Collection of Scholarly and Academic Papers >
Graduate School of Information Science and Technology / Faculty of Information Science and Technology >
Peer-reviewed Journal Articles, etc >

A 300 nW, 15 ppm/℃, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Files in This Item:
jssc_ueno2009.pdf1.12 MBPDFView/Open
Please use this identifier to cite or link to this item:http://hdl.handle.net/2115/39949

Title: A 300 nW, 15 ppm/℃, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
Other Titles: A 300 nW, 15 ppm/degC, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
Authors: Ueno, Ken1 Browse this author
Hirose, Tetsuya2 Browse this author
Asai, Tetsuya3 Browse this author
Amemiya, Yoshihito4 Browse this author →KAKEN DB
Authors(alt): Ueno, K.1
Hirose, T.2
Asai, T.3
Amemiya, Y.4
Keywords: CMOS
voltage reference
ultra-low power
subthreshold
weak inversion
process variation
die-to-die variation
power-aware LSIs
Issue Date: Jul-2009
Publisher: IEEE
Journal Title: IEEE Journal of Solid-State Circuits
Volume: 44
Issue: 7
Start Page: 2047
End Page: 2054
Publisher DOI: 10.1109/JSSC.2009.2021922
Abstract: A low-power CMOS voltage reference was developed using a 0.35 μm standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/℃ at best and 15 ppm/℃ on average, in a range from -20 to 80 ℃. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 μW at 80 ℃. The chip area was 0.05 mm2. Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
Rights: © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Type: article
URI: http://hdl.handle.net/2115/39949
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 上野 憲一

Export metadata:

OAI-PMH ( junii2 , jpcoar )

MathJax is now OFF:


 

Feedback - Hokkaido University