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Analog integrated circuits for the Lotka-Volterra competitive neural networks

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タイトル: Analog integrated circuits for the Lotka-Volterra competitive neural networks
著者: Asai, Tetsuya 著作を一覧する
Ohtani, Masashiro 著作を一覧する
Yonezu, Hiroo 著作を一覧する
発行日: 1999年 9月
出版者: IEEE
誌名: IEEE Transactions on Neural Networks
巻: 10
号: 5
開始ページ: 1222
終了ページ: 1231
出版社 DOI: 10.1109/72.788661
抄録: A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV ICs agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches
Rights: ©1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. IEEE, "IEEE Transactions on Neural Networks", 10-5, 1999, 1222-1231
資料タイプ: article
URI: http://hdl.handle.net/2115/5414
出現コレクション:雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

提供者: 浅井 哲也

 

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