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A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

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タイトル: A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy
著者: Miyoshi, Yoshihito 著作を一覧する
Nakajima, Fumito 著作を一覧する
Motohisa, Junichi 著作を一覧する
Fukuia, Takashi 著作を一覧する
発行日: 2005年 7月18日
出版者: American Institute of Physics
誌名: Applied Physics Letters
巻: 87
号: 3
開始ページ: 033501
出版社 DOI: 10.1063/1.1992665
抄録: We demonstrate single-electron operation of a 1 bit adder circuit using GaAs single-electron tunneling transistors (SETs). GaAs dot and wire coupled structures for the fabrication of SETs were grown by a selective-area metalorganic vapor-phase epitaxy technique. The logic circuit was realized based on a binary decision diagram architecture using Coulomb blockade (CB) in GaAs dots and switching operations were achieved in a single-electron mode because of the CB effects. Through this architecture, a 1 bit adder circuit was realized with three SETs, two of which were for AND logic and one with two input gates for exclusive OR (XOR). Both AND and XOR operations were demonstrated at 1.9 K, which indicated successful fabrication of the 1 bit adder.
Rights: Copyright © 2005 American Institute of Physics
資料タイプ: article
URI: http://hdl.handle.net/2115/5505
出現コレクション:雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

提供者: 本久 順一

 

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