A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

Miyoshi, Yoshihito; Nakajima, Fumito; Motohisa, Junichi; Fukuia, Takashi

doi:10.1063/1.1992665


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A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy

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Title:	A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy
Authors:	Miyoshi, Yoshihito Browse this author
	Nakajima, Fumito Browse this author
	Motohisa, Junichi³ Browse this author →KAKEN DB
	Fukuia, Takashi Browse this author
Authors(alt):	本久, 順一³
Issue Date:	18-Jul-2005
Publisher:	American Institute of Physics
Journal Title:	Applied Physics Letters
Volume:	87
Issue:	3
Start Page:	033501
Publisher DOI:	10.1063/1.1992665
Abstract:	We demonstrate single-electron operation of a 1 bit adder circuit using GaAs single-electron tunneling transistors (SETs). GaAs dot and wire coupled structures for the fabrication of SETs were grown by a selective-area metalorganic vapor-phase epitaxy technique. The logic circuit was realized based on a binary decision diagram architecture using Coulomb blockade (CB) in GaAs dots and switching operations were achieved in a single-electron mode because of the CB effects. Through this architecture, a 1 bit adder circuit was realized with three SETs, two of which were for AND logic and one with two input gates for exclusive OR (XOR). Both AND and XOR operations were demonstrated at 1.9 K, which indicated successful fabrication of the 1 bit adder.
Rights:	Copyright © 2005 American Institute of Physics
Type:	article
URI:	http://hdl.handle.net/2115/5505
Appears in Collections:	量子集積エレクトロニクス研究センター (Research Center for Integrated Quantum Electronics) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 本久順一

OAI-PMH ( junii2 , jpcoar_1.0 )

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