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Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

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Title: Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks
Authors: Takahagi, Kazuhiro Browse this author
Matsushita, Hiromichi Browse this author
Iida, Tomoki Browse this author
Ikebe, Masayuki Browse this author →KAKEN DB
Amemiya, Yoshihito Browse this author →KAKEN DB
Sano, Eiichi Browse this author →KAKEN DB
Keywords: Wake-up receiver
Envelope detector
High-gain amplifier
Clock and data recovery
Subthreshold operation
Issue Date: May-2013
Publisher: SPRINGER
Volume: 75
Issue: 2
Start Page: 199
End Page: 205
Publisher DOI: 10.1007/s10470-012-9929-1
Abstract: We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-mu m CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of -47.2 dBm while consuming only 6.8 mu W from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.
Rights: The final publication is available at
Type: article (author version)
Appears in Collections:量子集積エレクトロニクス研究センター (Research Center for Integrated Quantum Electronics) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 佐野 栄一

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