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Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth

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Title: Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth
Authors: Tomioka, Katsuhiro Browse this author →KAKEN DB
Fukui, Takashi Browse this author →KAKEN DB
Keywords: III-V nanowires
epitaxy
FET
tunnel FET
Issue Date: 1-Oct-2014
Publisher: IOP Publishing
Journal Title: Journal of Physics D: Applied Physics
Volume: 47
Issue: 39
Start Page: 394001
Publisher DOI: 10.1088/0022-3727/47/39/394001
Abstract: We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.
Rights: http://creativecommons.org/licenses/by/3.0
Type: article
URI: http://hdl.handle.net/2115/57448
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 福井 孝志

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