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TypeAuthor(s)TitleOther TitlesCitationCitation(alt)Issue Date
proceedings (author version)Kasai, Seiya; Amemiya, Yoshihito; Hasegawa, HidekiGaAs Schottky Wrap-Gate Binary-Decision-Diagram Devices for Realization of Novel Single Electron Logic Architecture---2000
articleAsai, Shin'ichi; Ueno, Ken; Asai, Tetsuya; Amemiya, YoshihitoHigh-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair-IEICE Transactions on Electronics-1-Jun-2010
articleTsugita, Yusuke; Ueno, Ken; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, YoshihitoAn On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs-IEICE Transactions on Electronics-1-Jun-2010
articleAsai, Tetsuya; Kanazawa, Yusuke; Amemiya, YoshihitoA subthreshold MOS neuron circuit based on the Volterra system-IEEE transactions on neural networks-Sep-2003
articleOgawa, Taichi; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, YoshihitoThreshold-Logic Devices Consisting of Subthreshold CMOS Circuits-IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences-1-Feb-2009
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