HUSCAP logo Hokkaido Univ. logo

Hokkaido University Collection of Scholarly and Academic Papers >
Graduate School of Information Science and Technology / Faculty of Information Science and Technology >
Peer-reviewed Journal Articles, etc >

Minimum-Width Method of Variable Ordering for Binary Decision Diagrams

Files in This Item:
62_IEICE75_392.pdf1.87 MBPDFView/Open
Please use this identifier to cite or link to this item:

Title: Minimum-Width Method of Variable Ordering for Binary Decision Diagrams
Authors: Minato, Shin-ichi Browse this author →KAKEN DB
Keywords: binary decision diagrams
boolean function
logic synthesis
variable ordering
Issue Date: 20-Mar-1992
Publisher: 電子情報通信学会
Journal Title: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E75
Issue: A3
Start Page: 392
End Page: 399
Abstract: Binary Decision Diagrams (BDDs) and Shared Binary Decision Diagrams (SBDDs), which are improved BDDs, are useful for implementing VLSI logic design systems. Recently, these representations, which are graph representations of Boolean functions, have become popular because of their efficiency in terms of time and space. The forms of the BDD vary with the order of the input variables though they represent the same function. The size of the graphs greatly depends on the order. The variable ordering algorithm is one of the most important issues in the application of BDDs. In this paper, we consider methods which reduce the graph size by reordering input variables on a given BDD with a certain variable order. We propose the Minimum-Width Method which gives a considerably good order in a practicable time and space. In the method, the order is determined by width of BDDs as a cost function. In addition, we show the effect of combining our method with the local search method, and also describe the improvement using the threshold. Experimental results show that our method can reduce the size of BDDs remarkably for most examples. The method needs no additional information, such as the topological information of the circuit. The results can be a measure for evaluation of other ordering methods.
Description: PAPER: Special Section on the 4th Karuizawa Workshop on Circuits and Systems
Rights: copyright©1992 IEICE
Type: article
Appears in Collections:情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)

Submitter: 湊 真一

Export metadata:

OAI-PMH ( junii2 , jpcoar_1.0 )

MathJax is now OFF:


 - Hokkaido University