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Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network
| Title: | Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network |
| Authors: | Kuroda, Ryota Browse this author | | Kasai, Seiya Browse this author →KAKEN DB |
| Keywords: | Word | | semiconductor nanowire network | | threshold logic | | hysteresis | | noise |
| Issue Date: | May-2017 |
| Publisher: | Taylor & Francis |
| Journal Title: | International journal of parallel, emergent and distributed systems |
| Volume: | 32 |
| Issue: | 3 |
| Start Page: | 287 |
| End Page: | 294 |
| Publisher DOI: | 10.1080/17445760.2016.1201673 |
| Abstract: | Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger. |
| Rights: | This is an Accepted Manuscript of an article published by Taylor & Francis in International journal of parallel, emergent and distributed systems on May 2017, available online: http://www.tandfonline.com/10.1080/17445760.2016.1201673. |
| Type: | article (author version) |
| URI: | http://hdl.handle.net/2115/70061 |
| Appears in Collections: | 量子集積エレクトロニクス研究センター (Research Center for Integrated Quantum Electronics) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 葛西 誠也
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